From 0d7b9f988b2160ca00a2d5f94b9f410a6f18b8f9 Mon Sep 17 00:00:00 2001 From: David Westgate Date: Thu, 10 Apr 2025 15:09:29 -0700 Subject: [PATCH] refactor + add menu --- __pycache__/init_regs_value.cpython-311.pyc | Bin 0 -> 755 bytes __pycache__/regs_addr.cpython-311.pyc | Bin 0 -> 5934 bytes __pycache__/util.cpython-311.pyc | Bin 0 -> 3668 bytes cc2500_init.json | 21 -- cc2500_regs.json | 97 ---------- init_regs_value.py | 42 ++++ main.py | 180 ++++-------------- receive.py | 40 ++++ regs_addr.py | 201 ++++++++++++++++++++ transmit.py | 17 ++ util.py | 65 +++++++ 11 files changed, 404 insertions(+), 259 deletions(-) create mode 100644 __pycache__/init_regs_value.cpython-311.pyc create mode 100644 __pycache__/regs_addr.cpython-311.pyc create mode 100644 __pycache__/util.cpython-311.pyc delete mode 100644 cc2500_init.json delete mode 100644 cc2500_regs.json create mode 100644 init_regs_value.py create mode 100644 regs_addr.py create mode 100644 util.py diff --git a/__pycache__/init_regs_value.cpython-311.pyc b/__pycache__/init_regs_value.cpython-311.pyc new file mode 100644 index 0000000000000000000000000000000000000000..b3c4f1841da08260d8433e762702f0934b932940 GIT binary patch literal 755 zcmZ9{&u$V?6bA4+zzhRrnDVcM7FybxG$huUX}i;y;0!d4g;s{RaMKXZq!LSM1~5@K zK7xr0H@Y;&ohx6#S7=z7xVmnfq#M(f=WyGGIE0ViH}~F?%NI?HGko6c{yq5=W$YJ~ znn%x zU1}CjQ9Rin;Z+yYuIkXtC~3 zktTZYtT#ILy_4bb%g*W8`^xBo?8-8p5Bi>Q-ZPv*cii{RMnj|98EuXHPWOf98~+`< zcmC>1eb67k_|$voS8#%a-{BvOAS_8za5tL?T|^S^oFI()8A+mKRG=`K93`tvrX4YI zTzHP05PLLoQdlR?3#Z6w;S4z|&gRGqOxAGbA~`SK7syLY*75x^xhPyBuL!S_%i`=B bd0lvee23)<7ukHUNrm0STb(}sCjRGtYJSWH literal 0 HcmV?d00001 diff --git a/__pycache__/regs_addr.cpython-311.pyc b/__pycache__/regs_addr.cpython-311.pyc new file mode 100644 index 0000000000000000000000000000000000000000..f937fb221aab11fac8babbaf90b1d53f72f6cd8c GIT binary patch literal 5934 zcmd6q$x~a&9mn58yFd#dHiK!>-rJE>oNamE^w_9pqi%Dj38hG#9pZ@*2f3II} zuk~l2&#Tej^sRp_ANn=zAIQ}Hf>n4o+N5cJ&}KBIF@05A(-(AIYtqIw*7T*uY3{HcEPv-6Fls?vUPP_ek%v2c#ddhoq0#W6}s4 zBaN~cX`CfU$JqpFl06}vWK*OmmL|=xY0{_6c%%POXC}+C88*wFu{k!+7TCw^6ZRAK zDa*0X_I>1EWY5_WV=T`;XUpsbTVY?Ymu!`-v30hw@BdE!CVRE-W1JP}e{0{y+SoSx z>3$RY8KpmGJ7oFAzH`BocjvwAmk($nuwR*4_}67jiLh>YvOAl37F$``T9T7QYHiNE z`=^c>me&?^rY$thXn9-S&UC~P)TGF!$gaqt$f?Ms$gRku$g8MXQHvsmC6b9ucEYe6 z=6pIjER!M2IX#)3il;3%rO~W0HLPgJvPWVu!*WI^BI&e20Zdt-3PYA7VZ@(~$bV}wj8ObnW9igC=?QETOt#sP?lrNMB%DjMQB6iR}qk&T;K z%P}ny7d=(xq10?7)NCX}>8~7?JC|EuT+8QjmN%DM+hE(P;FetO)%N0Q)ni*(-?9R^ z+~WHB#@6E2%Eo#jm-|Y4hlTv@mBAMqYx%*=mBHA?()L<@eXB6Iw77L`i!Uy{%=1A` zL!Db>j9=f};SQ=H1gpRBHLd*Ok^fRlpg38a+?_lIe8J*WacXy})a)-lDL&bKQU_Jb z-&#x+Q@g2>0(El83T8!lJoBBSvf2^B23(!^+v|Q#E-*}!cSa#Eho0LtM*|`iYaC0t`NRX9Q zm}N7KIg;!gnUk@pIGH1fC@C#n(&=Y0(gc+ur9v*)4O)J7Go6`E^PA|U`w-DzAAug# zWR#%rJCgU-fSR(6BcWWLmf}QlVt1mXKn;>A^L;=)qE;BIMK%?!Jbq|@Po5vw&@w*_ zXuxusv^i}TEZ20z$fjpfmTNX{m`NH^7dCwCinghzNy~1SX43McB1Y8AMzV3sO@o$A zrsA|oS82%d&{qcD8PoF4Ml-qDXf76sTCVKe*gS2XwBc5vnVyuZW{w~540RZX#ON;k zmgKzwSA)<9YItkoQwp>d)5Y{|y1vD!eM7l|?Zr$nvzsY325b$zwd49mD1jVoH17Dp zzD}O+KiJGp1L3fosr=do-@!m+BV)8^oY^^i(=DeV(&M}7Q+gDKm~e50N

L*O}vumpAR?mRX8AvbQkcB?{{49TRX0A?7bylef^bM zYD-x`bM1^%vtX^uJ{8Y!;z2HwG98>W?gr7%bB%jIHV}T%m+hctka(FEkf`eeApob} z`&tWXTjhA1q`i6WO!E)2O0!G2V}3b_WsA`SaE3UL(TD8x~SqYy_SjzWA8G6cbr z;vE#EF3sFlrc5Sn3`ow&GKCcre+yOiZYHAWgIEOe*Tye9)XNO zqL3IQ4oN`9Arp`!YnVDl(H zgkbrEZ9E6-XOKmba*-t5#2E~E7#>6ZMnYv@P{LOrU%=qxYv6Ur24oZR3c^V&kNRzq z4mVrQt)0!4^<^&Bfdhrm0`cJ$pB1rB%LTj&$6q1n%@5Y|x9$h>chE!rHFC9Usm!&R{l>Vb;ZD0@8zupZW3&vn1k6Py1f1 z(h6>q+zt+Dp1_{H(gE(2<-5S$GJX&EgyddupNxMJd`j|ZaKGd;;Ip#)Ij{y9kcRW% z3z9E_FG&uAFH61xzAE_|___={2p*C=3?7ku13W4leiM94+HZsJ$QQi}z9;!U_<`h) zzz^lK9)Tb0G855}8>{A`A{V0^dOt35;#Sdtm6p~H0I9etxq2m0lj)i& z5e$_A?YPK7eDtCa!BFL7AV~cPIje=b5tlA1PbE8gN@Ssnpz}o4)zw?+^#`a5q#sp8 z6Duw|jF1-D?ux_aCkw=@b@!FJdMU_}V%tqQy{oCBL5rT(cR;$x>rDqoSlY!G_&-d` BmW%)Z literal 0 HcmV?d00001 diff --git a/__pycache__/util.cpython-311.pyc b/__pycache__/util.cpython-311.pyc new file mode 100644 index 0000000000000000000000000000000000000000..8470d9c80df6f71e7927a46b3cf3c6b164ca3691 GIT binary patch literal 3668 zcmai1%WoUU8K312$>m$3TCzzKvN5(mEIQlNjvuCWJV0Tlsq%1wYSflv9q;X|aDxP#pv=bP8g z_xjE7%Rs)Bi!`8Ig%BWJs255drItjF1(!1c4}mEcVvt zkSzzuv`H30b~ecrWLJ~y1lipryFiwjWVa&9o+eoW+1n(06e|0gWUuW1glzfb0H9wE z0tVy|U{LM=49T5<9da13Q|8~cHWxPU!tb5sJL?<2vz>Pq5^EqXEG{l55;je2 zz#y84ufK1*f4jVqSY3~&goeckp->m$J^e2L7+S~+vLo-%n#TO0QU3zQyo9$}mdNj8 zAA+OuVxH>ss4=SEkH2j*LVSiZ@6w$*dC1+&s4V6kx+^a{?Ra`wcgT)fdsuUxttC^P z9O8=botKSoJrQ&POz4c;WM%WPeeT3(OO zJji90nZ5MPQZBWhRdzLXCY98tG?q*~RM^bEmd;G?9oW*2qHW`B)(5i#@Tz|SD3FRT zP*|$?Itok2L(%6sb7;mInmHlV8R1|`eMPA>QMq*a%jthlo0sOSOLHeg^gu6w=^rZI zDm|!#y35yIg@%pLaHYGyL@V9HCHnn|8;40m@)!4?C;N z%~yP(!rCcpgrw@(hXMu%50E*iJR>?eg5UO{3p+xqYamn6HIBpKgo3_^q;lD85^Ac( za`zN;(&FOW_1W3@SAy+)d|zR6F^4UxduiKU8>-?)A`yluX1l8M*a!&Npbh{O$T!se z*VQMh#Ye@oNqa2XW7Hqk4+B!T_j+jr`!#5JlPmQp)1Qq)17?r9m)lhp6}Jp_s2L)_l%$My;MQX?=tK{z z=%NBS4)>McF~cz{94oAS6AJ(1;BN=zD=(|I%EB3|w;Kh|ATWd&x25;jHWxQH-kW7nSQ`w0x-(?0n7|F7 z;znwk`sB2lyq8h7Q!K?Mp&jR_V*rr))hPb^pUO9^(D(~#1gA_oZP96?{Z02JRuuKM{<5jAACTG5Fv>W(kqTQBi@ya?p!IJbfj2VY||>p(zC z;}KntfNpFUMZjD*=X_7&#ADOYdl^Tdm%#D;m#zL;vwzO&2a{^Mu$>^Szoe89+ALhNW->K8K zeh;WsE3&JV4B^zpop3uqBDmwWdu4THee>1^&x6Atx;355L^$z94t<)UYIVVtdZ45p zMh-7-V&ev6|CK7G-sgvR%vp^gBmy2twsViAcQw`t4baJHbr$Njul5zZEZJWCMD^Na zJNXw>bTslzE&aOq2+lTV+I2`fU!VPdJg&|e$;4Z%kBHRKr1_XlKVY~4vmdT~6 zXDMEYt8P9|CGviDk6)hIJWP8BUUdrqoH{uEeA^tHwg#u+rsSOBU`o9}CDBUgB2dVM zk)tv5Le#ntEqb{5%Uz%DewH}u{ntm&KQeUOct_Fr2LtbWR zCnh1Fbr}BBVLk*u0$%#6VLpPjF$AtX9t)fb8Ac}8jd4~$_iYHup+wu$)Tun7#)u<)) z6`W0N?qKobPySq>l}5$eQR=n4{RQ_4^$Hy)qyaq+p%)mt4w6F{M6m`E6}sU{TL-@& dz%{o4E>QrsZ-Cb?44;q&3{U|)*bdxCKL93X@KXQ) literal 0 HcmV?d00001 diff --git a/cc2500_init.json b/cc2500_init.json deleted file mode 100644 index ff28853..0000000 --- a/cc2500_init.json +++ /dev/null @@ -1,21 +0,0 @@ -{ - "IOCFG0" : { "hex":"0x06", "dec":6}, - "PKTCTRL0": { "hex":"0x05", "dec":5}, - "FSCTRL1" : { "hex":"0x0A", "dec":10}, - "FREQ1" : { "hex":"0x20", "dec":32}, - "FREQ0" : { "hex":"0x11", "dec":17}, - "MDMCFG4" : { "hex":"0x2D", "dec":45}, - "MDMCFG3" : { "hex":"0x3B", "dec":59}, - "MDMCFG2" : { "hex":"0x73", "dec":115}, - "DEVIATN" : { "hex":"0x00", "dec":0}, - "MCSM0" : { "hex":"0x18", "dec":24}, - "FOCCFG" : { "hex":"0x1D", "dec":29}, - "BSCFG" : { "hex":"0x1C", "dec":28}, - "AGCCTRL2": { "hex":"0xC7", "dec":199}, - "AGCCTRL1": { "hex":"0x00", "dec":0}, - "AGCCTRL0": { "hex":"0xB0", "dec":176}, - "FREND1" : { "hex":"0xB6", "dec":182}, - "FSCAL3" : { "hex":"0xEA", "dec":234}, - "FSCAL1" : { "hex":"0x00", "dec":0}, - "FSCAL0" : { "hex":"0x11", "dec":17} -} \ No newline at end of file diff --git a/cc2500_regs.json b/cc2500_regs.json deleted file mode 100644 index a98a286..0000000 --- a/cc2500_regs.json +++ /dev/null @@ -1,97 +0,0 @@ -{ - "CONFIG_REGS": { - "IOCFG2": {"hex": "0x00", "dec": 0}, - "IOCFG1": {"hex": "0x01", "dec": 1}, - "IOCFG0": {"hex": "0x02", "dec": 2}, - "FIFOTHR": {"hex": "0x03", "dec": 3}, - "SYNC1": {"hex": "0x04", "dec": 4}, - "SYNC0": {"hex": "0x05", "dec": 5}, - "PKTLEN": {"hex": "0x06", "dec": 6}, - "PKTCTRL1": {"hex": "0x07", "dec": 7}, - "PKTCTRL0": {"hex": "0x08", "dec": 8}, - "ADDR": {"hex": "0x09", "dec": 9}, - "CHANNR": {"hex": "0x0A", "dec": 10}, - "FSCTRL1": {"hex": "0x0B", "dec": 11}, - "FSCTRL0": {"hex": "0x0C", "dec": 12}, - "FREQ2": {"hex": "0x0D", "dec": 13}, - "FREQ1": {"hex": "0x0E", "dec": 14}, - "FREQ0": {"hex": "0x0F", "dec": 15}, - "MDMCFG4": {"hex": "0x10", "dec": 16}, - "MDMCFG3": {"hex": "0x11", "dec": 17}, - "MDMCFG2": {"hex": "0x12", "dec": 18}, - "MDMCFG1": {"hex": "0x13", "dec": 19}, - "MDMCFG0": {"hex": "0x14", "dec": 20}, - "DEVIATN": {"hex": "0x15", "dec": 21}, - "MCSM2": {"hex": "0x16", "dec": 22}, - "MCSM1": {"hex": "0x17", "dec": 23}, - "MCSM0": {"hex": "0x18", "dec": 24}, - "FOCCFG": {"hex": "0x19", "dec": 25}, - "BSCFG": {"hex": "0x1A", "dec": 26}, - "AGCCTRL2": {"hex": "0x1B", "dec": 27}, - "AGCCTRL1": {"hex": "0x1C", "dec": 28}, - "AGCCTRL0": {"hex": "0x1D", "dec": 29}, - "WOREVT1": {"hex": "0x1E", "dec": 30}, - "WOREVT0": {"hex": "0x1F", "dec": 31}, - "WORCTRL": {"hex": "0x20", "dec": 32}, - "FREND1": {"hex": "0x21", "dec": 33}, - "FREND0": {"hex": "0x22", "dec": 34}, - "FSCAL3": {"hex": "0x23", "dec": 35}, - "FSCAL2": {"hex": "0x24", "dec": 36}, - "FSCAL1": {"hex": "0x25", "dec": 37}, - "FSCAL0": {"hex": "0x26", "dec": 38}, - "RCCTRL1": {"hex": "0x27", "dec": 39}, - "RCCTRL0": {"hex": "0x28", "dec": 40}, - "FSTEST": {"hex": "0x29", "dec": 41}, - "PTEST": {"hex": "0x2A", "dec": 42}, - "AGCTEST": {"hex": "0x2B", "dec": 43}, - "TEST2": {"hex": "0x2C", "dec": 44}, - "TEST1": {"hex": "0x2D", "dec": 45}, - "TEST0": {"hex": "0x2E", "dec": 46} - }, - "STROBES": { - "SRES": {"hex": "0x30", "dec": 48}, - "SFSTXON": {"hex": "0x31", "dec": 49}, - "SXOFF": {"hex": "0x32", "dec": 50}, - "SCAL": {"hex": "0x33", "dec": 51}, - "SRX": {"hex": "0x34", "dec": 52}, - "STX": {"hex": "0x35", "dec": 53}, - "SIDLE": {"hex": "0x36", "dec": 54}, - "SAFC": {"hex": "0x37", "dec": 55}, - "SWOR": {"hex": "0x38", "dec": 56}, - "SPWD": {"hex": "0x39", "dec": 57}, - "SFRX": {"hex": "0x3A", "dec": 58}, - "SFTX": {"hex": "0x3B", "dec": 59}, - "SWORRST": {"hex": "0x3C", "dec": 60}, - "SNOP": {"hex": "0x3D", "dec": 61} - }, - "STATUS": { - "PARTNUM": {"hex": "0x30", "dec": 48}, - "VERSION": {"hex": "0x31", "dec": 49}, - "FREQEST": {"hex": "0x32", "dec": 50}, - "LQI": {"hex": "0x33", "dec": 51}, - "RSSI": {"hex": "0x34", "dec": 52}, - "MARCSTATE": {"hex": "0x35", "dec": 53}, - "WORTIME1": {"hex": "0x36", "dec": 54}, - "WORTIME0": {"hex": "0x37", "dec": 55}, - "PKTSTATUS": {"hex": "0x38", "dec": 56}, - "VCO_VC_DAC": {"hex": "0x39", "dec": 57}, - "TXBYTES": {"hex": "0x3A", "dec": 58}, - "RXBYTES": {"hex": "0x3B", "dec": 59}, - "NUM_RXBYTES": {"hex": "0x7F", "dec": 127} - }, - "MEMORY": { - "PATABLE": {"hex": "0x3E", "dec": 62}, - "TXFIFO": {"hex": "0x3F", "dec": 63}, - "RXFIFO": {"hex": "0x3F", "dec": 63} - }, - "MASKS": { - "LQI_RX": {"hex": "0x01", "dec": 1}, - "CRC_OK": {"hex": "0x80", "dec": 128} - }, - "ACCESS": { - "WRITE_BURST": {"hex": "0x40", "dec": 64}, - "READ_SINGLE": {"hex": "0x80", "dec": 128}, - "READ_BURST": {"hex": "0xC0", "dec": 192} - } - -} diff --git a/init_regs_value.py b/init_regs_value.py new file mode 100644 index 0000000..7ed3cf3 --- /dev/null +++ b/init_regs_value.py @@ -0,0 +1,42 @@ +# Address Config = No address check +# Base Frequency = 2447.256836 +# CRC Autoflush = false +# CRC Enable = true +# Carrier Frequency = 2447.256836 +# Channel Number = 0 +# Channel Spacing = 199.951172 +# Data Format = Normal mode +# Data Rate = 249.939 +# Device Address = 0 +# Manchester Enable = false +# Modulated = true +# Modulation Format = MSK +# Packet Length = 255 +# Packet Length Mode = Variable packet length mode. Packet length configured by the first byte after sync word +# Phase Transition Time = 0 +# Preamble Count = 4 +# RX Filter BW = 541.666667 +# Sync Word Qualifier Mode = 30/32 sync word bits detected +# TX Power = 0 +# Whitening = false +init_regs_value = { + "IOCFG0" : 0x06, # 6 - GDO0OUTPUT PIN CONFIGURATION + "PKTCTRL0": 0x05, # 5 - PACKET AUTOMATION CONTROL + "FSCTRL1" : 0x12, # 18 - FREQUENCY SYNTHESIZER CONTROL + "FREQ1" : 0x20, # 32 - FREQUENCY CONTROL WORD, MIDDLE BYTE + "FREQ0" : 0x11, # 17 - FREQUENCY CONTROL WORD, LOW BYTE + "MDMCFG4" : 0x2D, # 45 - MODEM CONFIGURATION + "MDMCFG3" : 0x3B, # 59 - MODEM CONFIGURATION + "MDMCFG2" : 0xF3, # 243 - MODEM CONFIGURATION + "DEVIATN" : 0x00, # 0 - MODEM DEVIATION SETTING + "MCSM0" : 0x18, # 24 - MAIN RADIO CONTROL STATE MACHINE CONFIGURATION + "FOCCFG" : 0x1D, # 29 - FREQUENCY OFFSET COMPENSATION CONFIGURATION + "BSCFG" : 0x1C, # 28 - BIT SYNCHRONIZATION CONFIGURATION + "AGCCTRL2": 0xC7, # 199 - AGC CONTROL + "AGCCTRL1": 0x00, # 0 - AGC CONTROL + "AGCCTRL0": 0xB0, # 176 - AGC CONTROL + "FREND1" : 0xB6, # 182 - FRONT END RX CONFIGURATION + "FSCAL3" : 0xEA, # 234 - FREQUENCY SYNTHESIZER CALIBRATION + "FSCAL1" : 0x00, # 0 - FREQUENCY SYNTHESIZER CALIBRATION + "FSCAL0" : 0x11, # 17 - FREQUENCY SYNTHESIZER CALIBRATION +} \ No newline at end of file diff --git a/main.py b/main.py index a01b6eb..43c4280 100644 --- a/main.py +++ b/main.py @@ -1,136 +1,25 @@ import spidev +import sys +import select import time -import json - -# Initialize SPI -global spi -global init_data -# global regs_data -global CONFIG_REGS -global STROBES -global STATUS -global MEMORY -global MASKS -global ACCESS -def asb (a): - return int(a,16) +from init_regs_value import init_regs_value +from regs_addr import regs_addr +from util import * +debug = True -def strobe(command): - """Send a command strobe to CC2500""" - spi.xfer2([command]) - -def write_reg(addr, value): - """Write single byte to a register""" - spi.xfer2([addr, value]) - -def burst_write(addr, data): - """Write multiple bytes to FIFO or registers""" - BURST = 0x40 - spi.xfer2([addr | BURST] + data) - -def burst_read(addr, length): - """Read multiple bytes""" - READ_SINGLE = ACCESS["READ_SINGLE"]["dec"] - READ_BURST = ACCESS["READ_BURST"]["dec"] - return spi.xfer2([addr | READ_SINGLE | READ_BURST] + [0x00] * length) - -def read_fifo(): - # Burst read RX FIFO - READ_BURST = ACCESS["READ_BURST"]["dec"] - RXFIFO = MEMORY["RXFIFI"]["dec"] - fifo = spi.xfer2([RXFIFO | READ_BURST] + [0x00]*64) # Max 64 bytes - return fifo[1:] - - -def read_register(addr): - READ_SINGLE = ACCESS["READ_SINGLE"]["dec"] - # Send address | 0x80 (read), then 0x00 dummy to clock in response - response = spi.xfer2([READ_SINGLE | addr, 0x00]) - return response[1] - -def send_packet(data): - # Flush TX FIFO - strobe(0x3B) # SFTX - - # Load data to TX FIFO (fixed length) - burst_write(0x3F, data) # 0x3F = TX FIFO - - # Strobe STX to transmit - strobe(0x35) # STX - - print(f"Sent: {data}") - - -def receive_packet(): - # Flush RX FIFO - SFRX = STROBES["SFRX"]["dec"] - strobe(SFRX) # SFRX - - SRX = STROBES["SRX"]["dec"] - # Go into RX mode - strobe(SRX) # SRX - - # Wait for data (use GDO0 in real app) - time.sleep(0.5) - - # Check RXBYTES - RXBYTES = STATUS["RXBYTES"]["dec"] - rx_bytes = read_register(RXBYTES) & 0x7F - if rx_bytes == 0: - print("No data received.") - return None - - # Read data - RXFIFO = MEMORY["RXFIFO"]["dec"] - data = read_fifo() # 0x3F = RX FIFO - print(f"Received: {data}") - return data - -def test_read_write_reg(): - FIFOTHR = CONFIG_REGS["FIFOTHR"]["dec"] - print("reg ", hex(FIFOTHR)) - initial_val = read_register(FIFOTHR) - test_value = initial_val + 1 - write_reg(FIFOTHR, test_value) - check = read_register(FIFOTHR) - write_reg(FIFOTHR, initial_val) - print("initial value ", initial_val) - print("test value ", test_value) - print("check ",check) - return check == test_value - -def disable_crc(): - spi.xfer2([CONFIG_REGS["PKTCTRL0"]["dec"], 0x01]) - -def dump_reg(): - for reg_name_group, regs in regs_data.items(): - for reg_name, reg_loc in regs.items(): - addr = reg_loc['dec'] - reg_value = read_register(addr) - print(reg_name + ":"+str(reg_value)) +def menu(): + print("\nMenu") + print("1: Read Reg by name") + print("2: Write reg hex value by name") + print("0: Quit") if __name__ == "__main__": spi = spidev.SpiDev() spi.open(0, 0) # Bus 0, CE0 (Pin 24) spi.max_speed_hz = 2000000 # Safe start speed spi.mode = 0b00 # SPI mode 0 - - - with open("cc2500_init.json", "r") as f: - init_data = json.load(f) - with open("cc2500_regs.json", "r") as f: - regs_data = json.load(f) - CONFIG_REGS = regs_data["CONFIG_REGS"] - STROBES = regs_data["STROBES"] - STATUS = regs_data["STATUS"] - MEMORY = regs_data["MEMORY"] - MASKS = regs_data["MASKS"] - ACCESS = regs_data["ACCESS"] - - SRES = STROBES["SRES"]["dec"] - SNOP = STROBES["SNOP"]["dec"] - VERSION = STATUS["VERSION"]["dec"] + stop = False print("Sending SRES (reset)...") spi.xfer2([SRES]) @@ -141,27 +30,36 @@ if __name__ == "__main__": print(f"Status byte: 0x{status:02X}") print("Reading VERSION register...") - version = read_register(VERSION) + version = read_register(spi, VERSION) print(f"CC2500 VERSION register: 0x{version:02X}") - # dump_reg() + init_regs(spi) + time.sleep(0.1) - for reg_name, values in init_data.items(): - addr_dec = regs_data["CONFIG_REGS"][reg_name]["dec"] - addr_hex = regs_data["CONFIG_REGS"][reg_name]["hex"] - value_hex = values["hex"] - value_dec = values["dec"] - # print(addr) - # print(values["hex"]) - # print("writing "+str(addr_hex) + " to "+str(addr_dec)) - write_reg(addr_dec, value_dec) - disable_crc() - time.sleep(2) - # dump_reg() - print("Read + Write test ", test_read_write_reg()) + test_read_write_reg(spi) + + reg_name = "" + reg_hex_val = "" try: - while True: - receive_packet() - time.sleep(1) + while not stop: + menu() + cmd = int(input("$: ")) + if cmd == 0: + stop=True + elif cmd == 1: + reg_name = input("Register name: ") + addr = get_addr(reg_name) + value = read_register(spi,addr) + print("Address: " + hex(addr)+ ", Value: " + hex(value) +" == " + str(value)) + elif cmd == 2: + reg_name = input("Register name: ") + addr = get_addr(reg_name) + value = int(input("New Register value (hex): "),16) + write_reg(spi, addr, value) + time.sleep(0.1) + value_check = read_register(spi,addr) + print("Updated Value: " + hex(value) +" == " + str(value)) + else: + print("Invalid command") finally: spi.close() diff --git a/receive.py b/receive.py index e69de29..958070e 100644 --- a/receive.py +++ b/receive.py @@ -0,0 +1,40 @@ +def burst_read(addr, length): + """Read multiple bytes""" + READ_SINGLE = ACCESS["READ_SINGLE"]["dec"] + READ_BURST = ACCESS["READ_BURST"]["dec"] + return spi.xfer2([addr | READ_SINGLE | READ_BURST] + [0x00] * length) + + + +def read_fifo(): + # Burst read RX FIFO + READ_BURST = ACCESS["READ_BURST"]["dec"] + RXFIFO = MEMORY["RXFIFI"]["dec"] + fifo = spi.xfer2([RXFIFO | READ_BURST] + [0x00]*64) # Max 64 bytes + return fifo[1:] + + +def receive_packet(): + # Flush RX FIFO + SFRX = STROBES["SFRX"]["dec"] + strobe(SFRX) # SFRX + + SRX = STROBES["SRX"]["dec"] + # Go into RX mode + strobe(SRX) # SRX + + # Wait for data (use GDO0 in real app) + time.sleep(0.5) + + # Check RXBYTES + RXBYTES = STATUS["RXBYTES"]["dec"] + rx_bytes = read_register(RXBYTES) & 0x7F + if rx_bytes == 0: + print("No data received.") + return None + + # Read data + RXFIFO = MEMORY["RXFIFO"]["dec"] + data = read_fifo() # 0x3F = RX FIFO + print(f"Received: {data}") + return data diff --git a/regs_addr.py b/regs_addr.py new file mode 100644 index 0000000..4a25151 --- /dev/null +++ b/regs_addr.py @@ -0,0 +1,201 @@ +from typing import TypedDict + +class ConfigRegs(TypedDict): + IOCFG2: int + IOCFG1: int + IOCFG0: int + FIFOTHR: int + SYNC1: int + SYNC0: int + PKTLEN: int + PKTCTRL1: int + PKTCTRL0: int + ADDR: int + CHANNR: int + FSCTRL1: int + FSCTRL0: int + FREQ2: int + FREQ1: int + FREQ0: int + MDMCFG4: int + MDMCFG3: int + MDMCFG2: int + MDMCFG1: int + MDMCFG0: int + DEVIATN: int + MCSM2: int + MCSM1: int + MCSM0: int + FOCCFG: int + BSCFG: int + AGCCTRL2: int + AGCCTRL1: int + AGCCTRL0: int + WOREVT1: int + WOREVT0: int + WORCTRL: int + FREND1: int + FREND0: int + FSCAL3: int + FSCAL2: int + FSCAL1: int + FSCAL0: int + RCCTRL1: int + RCCTRL0: int + FSTEST: int + PTEST: int + AGCTEST: int + TEST2: int + TEST1: int + TEST0: int + +class Strobes(TypedDict): + SRES: int + SFSTXON: int + SXOFF: int + SCAL: int + SRX: int + STX: int + SIDLE: int + SAFC: int + SWOR: int + SPWD: int + SFRX: int + SFTX: int + SWORRST: int + SNOP: int + +class Status(TypedDict): + PARTNUM: int + VERSION: int + FREQEST: int + LQI: int + RSSI: int + MARCSTATE: int + WORTIME1: int + WORTIME0: int + PKTSTATUS: int + VCO_VC_DAC: int + TXBYTES: int + RXBYTES: int + NUM_RXBYTES: int + +class Memory(TypedDict): + PATABLE: int + TXFIFO: int + RXFIFO: int + +class Masks(TypedDict): + LQI_RX: int + CRC_OK: int + +class Access(TypedDict): + WRITE_BURST: int + READ_SINGLE: int + READ_BURST: int + +class RegsAddr(TypedDict): + CONFIG_REGS: ConfigRegs + STROBES: Strobes + STATUS: Status + MEMORY: Memory + MASKS: Masks + ACCESS: Access + + +regs_addr: RegsAddr = { + "CONFIG_REGS": { + "IOCFG2": 0x00, + "IOCFG1": 0x01, + "IOCFG0": 0x02, + "FIFOTHR": 0x03, + "SYNC1": 0x04, + "SYNC0": 0x05, + "PKTLEN": 0x06, + "PKTCTRL1": 0x07, + "PKTCTRL0": 0x08, + "ADDR": 0x09, + "CHANNR": 0x0A, + "FSCTRL1": 0x0B, + "FSCTRL0": 0x0C, + "FREQ2": 0x0D, + "FREQ1": 0x0E, + "FREQ0": 0x0F, + "MDMCFG4": 0x10, + "MDMCFG3": 0x11, + "MDMCFG2": 0x12, + "MDMCFG1": 0x13, + "MDMCFG0": 0x14, + "DEVIATN": 0x15, + "MCSM2": 0x16, + "MCSM1": 0x17, + "MCSM0": 0x18, + "FOCCFG": 0x19, + "BSCFG": 0x1A, + "AGCCTRL2": 0x1B, + "AGCCTRL1": 0x1C, + "AGCCTRL0": 0x1D, + "WOREVT1": 0x1E, + "WOREVT0": 0x1F, + "WORCTRL": 0x20, + "FREND1": 0x21, + "FREND0": 0x22, + "FSCAL3": 0x23, + "FSCAL2": 0x24, + "FSCAL1": 0x25, + "FSCAL0": 0x26, + "RCCTRL1": 0x27, + "RCCTRL0": 0x28, + "FSTEST": 0x29, + "PTEST": 0x2A, + "AGCTEST": 0x2B, + "TEST2": 0x2C, + "TEST1": 0x2D, + "TEST0": 0x2E + }, + "STROBES": { + "SRES": 0x30, + "SFSTXON": 0x31, + "SXOFF": 0x32, + "SCAL": 0x33, + "SRX": 0x34, + "STX": 0x35, + "SIDLE": 0x36, + "SAFC": 0x37, + "SWOR": 0x38, + "SPWD": 0x39, + "SFRX": 0x3A, + "SFTX": 0x3B, + "SWORRST": 0x3C, + "SNOP": 0x3D + }, + "STATUS": { + "PARTNUM": 0x30, + "VERSION": 0x31, + "FREQEST": 0x32, + "LQI": 0x33, + "RSSI": 0x34, + "MARCSTATE": 0x35, + "WORTIME1": 0x36, + "WORTIME0": 0x37, + "PKTSTATUS": 0x38, + "VCO_VC_DAC": 0x39, + "TXBYTES": 0x3A, + "RXBYTES": 0x3B, + "NUM_RXBYTES": 0x7F + }, + "MEMORY": { + "PATABLE": 0x3E, + "TXFIFO": 0x3F, + "RXFIFO": 0x3F + }, + "MASKS": { + "LQI_RX": 0x01, + "CRC_OK": 0x80 + }, + "ACCESS": { + "WRITE_BURST": 0x40, + "READ_SINGLE": 0x80, + "READ_BURST": 0xC0 + } +} diff --git a/transmit.py b/transmit.py index e69de29..124b136 100644 --- a/transmit.py +++ b/transmit.py @@ -0,0 +1,17 @@ +def burst_write(addr, data): + """Write multiple bytes to FIFO or registers""" + BURST = 0x40 + spi.xfer2([addr | BURST] + data) + + +def send_packet(data): + # Flush TX FIFO + strobe(0x3B) # SFTX + + # Load data to TX FIFO (fixed length) + burst_write(0x3F, data) # 0x3F = TX FIFO + + # Strobe STX to transmit + strobe(0x35) # STX + + print(f"Sent: {data}") diff --git a/util.py b/util.py new file mode 100644 index 0000000..aeda58e --- /dev/null +++ b/util.py @@ -0,0 +1,65 @@ +from init_regs_value import init_regs_value +from regs_addr import regs_addr +CONFIG_REGS = regs_addr["CONFIG_REGS"] +STROBES = regs_addr["STROBES"] +STATUS = regs_addr["STATUS"] +MEMORY = regs_addr["MEMORY"] +MASKS = regs_addr["MASKS"] +ACCESS = regs_addr["ACCESS"] +SRES = STROBES["SRES"] +SNOP = STROBES["SNOP"] +VERSION = STATUS["VERSION"] + +def get_addr(name): + addr = "" + stop = False + for reg_type, reg_data in regs_addr.items(): + for reg_name, reg_addr in reg_data.items(): + if reg_name == name: + stop = True + addr = reg_addr + if stop == False: + raise Exception("Failed to find address for "+name) + return addr + +def strobe(spi, command): + """Send a command strobe to CC2500""" + spi.xfer2([command]) + +def write_reg(spi, addr, value): + """Write single byte to a register""" + spi.xfer2([addr, value]) + +def read_register(spi, addr): + READ_SINGLE = get_addr("READ_SINGLE") + # Send address | 0x80 (read), then 0x00 dummy to clock in response + response = spi.xfer2([READ_SINGLE | addr, 0x00]) + return response[1] + +def disable_crc(spi): + spi.xfer2([CONFIG_REGS["PKTCTRL0"], 0x01]) + +def init_regs(spi): + for reg_name, value in init_regs_value.items(): + addr = get_addr(reg_name) + write_reg(spi, addr, value) + +def test_read_write_reg(spi): + FIFOTHR = get_addr("FIFOTHR") + initial_val = read_register(spi, FIFOTHR) + test_value = initial_val + 1 + write_reg(spi, FIFOTHR, test_value) + check = read_register(spi, FIFOTHR) + write_reg(spi, FIFOTHR, initial_val) + if check != test_value: + print("initial value ", initial_val) + print("test value ", test_value) + print("check ",check) + raise Exception("Test Read+Write failed") + return check == test_value + +def dump_regs(): + for reg_name, reg_loc in regs_addr.items(): + addr = reg_loc + reg_value = read_register(addr) + print(reg_name + ":"+str(reg_value)) \ No newline at end of file