diff --git a/.vscode/settings.json b/.vscode/settings.json
new file mode 100644
index 0000000..c1860fa
--- /dev/null
+++ b/.vscode/settings.json
@@ -0,0 +1,3 @@
+{
+ 
+}
\ No newline at end of file
diff --git a/__init__.py b/src/__init__.py
similarity index 100%
rename from __init__.py
rename to src/__init__.py
diff --git a/common.py b/src/common.py
similarity index 95%
rename from common.py
rename to src/common.py
index dfd9c6f..ee5b570 100644
--- a/common.py
+++ b/src/common.py
@@ -1,8 +1,8 @@
 import spidev
 import RPi.GPIO as GPIO
-from util import sleep, get_addr
-from init_regs_value import init_regs_value
-from regs_addr import regs_addr
+from .util import sleep, get_addr
+from .init_regs_value import init_regs_value
+from .regs_addr import regs_addr
 CONFIG_REGS = regs_addr["CONFIG_REGS"]
 STROBES = regs_addr["STROBES"]
 STATUS = regs_addr["STATUS"]
diff --git a/init_regs_value.py b/src/init_regs_value.py
similarity index 100%
rename from init_regs_value.py
rename to src/init_regs_value.py
diff --git a/main.py b/src/main.py
similarity index 86%
rename from main.py
rename to src/main.py
index 957af31..52ece6c 100644
--- a/main.py
+++ b/src/main.py
@@ -1,8 +1,8 @@
 import spidev
-from util import print_gdo_state, sleep, get_addr, dump_regs, debug, GDO0_PIN, GDO2_PIN
-from receive import rx_data_rf
-from transmit import transmit_packet
-from common import reset, setup_spi, setup_gpio, read_register, test_read_write_reg, init_cc_2500, write_reg, SRES, SNOP, MARCSTATE, VERSION
+from .util import print_gdo_state, sleep, get_addr, dump_regs, debug, GDO0_PIN, GDO2_PIN
+from .receive import rx_data_rf
+from .transmit import transmit_packet
+from .common import reset, setup_spi, setup_gpio, read_register, test_read_write_reg, init_cc_2500, write_reg, SRES, SNOP, MARCSTATE, VERSION
 
 
 
diff --git a/receive.py b/src/receive.py
similarity index 96%
rename from receive.py
rename to src/receive.py
index f05b5fa..d8a3ba5 100644
--- a/receive.py
+++ b/src/receive.py
@@ -1,6 +1,6 @@
-from util import sleep, get_addr, digital_read, GDO0_PIN, GDO2_PIN, debug, delay
+from .util import sleep, get_addr, digital_read, GDO0_PIN, GDO2_PIN, debug, delay
 import time
-from common import strobe, read_register
+from .common import strobe, read_register
 
 SIDLE = get_addr('SIDLE')
 SFRX = get_addr('SFRX')
diff --git a/regs_addr.py b/src/regs_addr.py
similarity index 100%
rename from regs_addr.py
rename to src/regs_addr.py
diff --git a/transmit.py b/src/transmit.py
similarity index 83%
rename from transmit.py
rename to src/transmit.py
index 0b5f3fe..086cd1e 100644
--- a/transmit.py
+++ b/src/transmit.py
@@ -1,5 +1,5 @@
-from common import strobe, write_burst
-from util import get_addr
+from .common import strobe, write_burst
+from .util import get_addr
 
 
 SIDLE = get_addr('SIDLE')
diff --git a/util.py b/src/util.py
similarity index 98%
rename from util.py
rename to src/util.py
index 44d53d4..f6852a1 100644
--- a/util.py
+++ b/src/util.py
@@ -1,4 +1,4 @@
-from regs_addr import regs_addr
+from .regs_addr import regs_addr
 import RPi.GPIO as GPIO
 import time
 debug = True