code tweaks

This commit is contained in:
David Westgate 2025-04-10 18:59:11 -07:00
parent f034d91fa9
commit a7327f294e
3 changed files with 34 additions and 26 deletions

17
main.py
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@ -9,18 +9,19 @@ def menu():
print("2: Write reg hex value by name") print("2: Write reg hex value by name")
print("3: Dump registers") print("3: Dump registers")
print("4: Poll for packets") print("4: Poll for packets")
print("5: Run Read+Write test")
print("0: Quit") print("0: Quit")
if __name__ == "__main__": if __name__ == "__main__":
spi = spidev.SpiDev() spi = spidev.SpiDev()
spi.open(0, 0) # Bus 0, CE0 (Pin 24) spi.open(0, 0) # Bus 0, CE0 (Pin 24)
spi.max_speed_hz = 500000 # Safe start speed spi.max_speed_hz = 8000000 # Safe start speed
spi.mode = 0b00 # SPI mode 0 spi.mode = 0b00 # SPI mode 0
stop = False stop = False
print("Sending SRES (reset)...") print("Sending SRES (reset)...")
spi.xfer2([SRES]) spi.xfer2([SRES])
sleep(0.1) sleep(0.5)
print("Sending SNOP (no-op)...") print("Sending SNOP (no-op)...")
status = spi.xfer2([SNOP])[0] status = spi.xfer2([SNOP])[0]
@ -30,10 +31,12 @@ if __name__ == "__main__":
version = read_register(spi, VERSION) version = read_register(spi, VERSION)
print(f"CC2500 VERSION register: 0x{version:02X}") print(f"CC2500 VERSION register: 0x{version:02X}")
test_read_write_reg(spi)
init_regs(spi) init_regs(spi)
sleep(0.1) sleep(0.1)
test_read_write_reg(spi)
reg_name = "" reg_name = ""
reg_hex_val = "" reg_hex_val = ""
@ -59,10 +62,12 @@ if __name__ == "__main__":
elif cmd == 3: elif cmd == 3:
dump_regs(spi) dump_regs(spi)
elif cmd == 4: elif cmd == 4:
while True: receive_packet(spi)
receive_packet(spi) elif cmd == 5:
sleep(0.2) res = test_read_write_reg(spi, True)
print("Test result : "+str(res))
else: else:
print("Invalid command") print("Invalid command")
finally: finally:
print("Closing SPI...")
spi.close() spi.close()

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@ -3,8 +3,8 @@ import time
def burst_read(spi, addr, length): def burst_read(spi, addr, length):
"""Read multiple bytes""" """Read multiple bytes"""
READ_SINGLE = get_addr["READ_SINGLE"] READ_SINGLE = get_addr("READ_SINGLE")
READ_BURST = get_addr["READ_BURST"] READ_BURST = get_addr("READ_BURST")
return spi.xfer2([addr | READ_SINGLE | READ_BURST] + [0x00] * length) return spi.xfer2([addr | READ_SINGLE | READ_BURST] + [0x00] * length)
@ -18,26 +18,28 @@ def read_fifo(spi):
def receive_packet(spi): def receive_packet(spi):
# Flush RX FIFO
SFRX = get_addr("SFRX") SFRX = get_addr("SFRX")
strobe(spi, SFRX) # SFRX RXBYTES = get_addr("RXBYTES")
SRX = get_addr("SRX")
SRX = get_addr( "SRX")
# Flush RX FIFO
strobe(spi, SFRX)
time.sleep(0.5) # 1 ms delay to allow flush
# Go into RX mode # Go into RX mode
strobe(spi, SRX) # SRX strobe(spi, SRX)
# Wait for data (use GDO0 in real app) # Wait for data (use GDO0 in real app)
time.sleep(0.5) sleep(0.5)
# Check RXBYTES # Check RXBYTES
RXBYTES = get_addr( "RXBYTES")
rx_bytes = read_register(spi, RXBYTES) & 0x7F timeout = time.time() + 2 # 2-second timeout
if rx_bytes == 0: while time.time() < timeout:
print("No data received.") rx_bytes = read_register(spi, RXBYTES) & 0x7F
return None if rx_bytes > 0:
data = read_fifo(spi)
print(f"Received: {data}")
return data
time.sleep(0.01)
# Read data print("Timeout: no data received.")
# RXFIFO = get_addr("RXFIFO")
data = read_fifo(spi) # 0x3F = RX FIFO
print(f"Received: {data}")
return data

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@ -45,17 +45,18 @@ def init_regs(spi):
addr = get_addr(reg_name) addr = get_addr(reg_name)
write_reg(spi, addr, value) write_reg(spi, addr, value)
def test_read_write_reg(spi): def test_read_write_reg(spi, dbg=False):
FIFOTHR = get_addr("FIFOTHR") FIFOTHR = get_addr("FIFOTHR")
initial_val = read_register(spi, FIFOTHR) initial_val = read_register(spi, FIFOTHR)
test_value = initial_val + 1 test_value = initial_val + 1
write_reg(spi, FIFOTHR, test_value) write_reg(spi, FIFOTHR, test_value)
check = read_register(spi, FIFOTHR) check = read_register(spi, FIFOTHR)
write_reg(spi, FIFOTHR, initial_val) write_reg(spi, FIFOTHR, initial_val)
if check != test_value: if(dbg):
print("initial value ", initial_val) print("initial value ", initial_val)
print("test value ", test_value) print("test value ", test_value)
print("check ",check) print("check ",check)
elif (not dbg and (check != test_value)):
raise Exception("Test Read+Write failed") raise Exception("Test Read+Write failed")
return check == test_value return check == test_value