code tweaks
This commit is contained in:
parent
f034d91fa9
commit
a7327f294e
17
main.py
17
main.py
@ -9,18 +9,19 @@ def menu():
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print("2: Write reg hex value by name")
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print("2: Write reg hex value by name")
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print("3: Dump registers")
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print("3: Dump registers")
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print("4: Poll for packets")
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print("4: Poll for packets")
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print("5: Run Read+Write test")
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print("0: Quit")
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print("0: Quit")
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if __name__ == "__main__":
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if __name__ == "__main__":
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spi = spidev.SpiDev()
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spi = spidev.SpiDev()
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spi.open(0, 0) # Bus 0, CE0 (Pin 24)
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spi.open(0, 0) # Bus 0, CE0 (Pin 24)
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spi.max_speed_hz = 500000 # Safe start speed
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spi.max_speed_hz = 8000000 # Safe start speed
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spi.mode = 0b00 # SPI mode 0
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spi.mode = 0b00 # SPI mode 0
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stop = False
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stop = False
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print("Sending SRES (reset)...")
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print("Sending SRES (reset)...")
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spi.xfer2([SRES])
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spi.xfer2([SRES])
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sleep(0.1)
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sleep(0.5)
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print("Sending SNOP (no-op)...")
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print("Sending SNOP (no-op)...")
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status = spi.xfer2([SNOP])[0]
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status = spi.xfer2([SNOP])[0]
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@ -30,10 +31,12 @@ if __name__ == "__main__":
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version = read_register(spi, VERSION)
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version = read_register(spi, VERSION)
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print(f"CC2500 VERSION register: 0x{version:02X}")
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print(f"CC2500 VERSION register: 0x{version:02X}")
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test_read_write_reg(spi)
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init_regs(spi)
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init_regs(spi)
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sleep(0.1)
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sleep(0.1)
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test_read_write_reg(spi)
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reg_name = ""
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reg_name = ""
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reg_hex_val = ""
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reg_hex_val = ""
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@ -59,10 +62,12 @@ if __name__ == "__main__":
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elif cmd == 3:
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elif cmd == 3:
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dump_regs(spi)
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dump_regs(spi)
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elif cmd == 4:
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elif cmd == 4:
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while True:
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receive_packet(spi)
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receive_packet(spi)
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elif cmd == 5:
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sleep(0.2)
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res = test_read_write_reg(spi, True)
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print("Test result : "+str(res))
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else:
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else:
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print("Invalid command")
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print("Invalid command")
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finally:
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finally:
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print("Closing SPI...")
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spi.close()
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spi.close()
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38
receive.py
38
receive.py
@ -3,8 +3,8 @@ import time
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def burst_read(spi, addr, length):
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def burst_read(spi, addr, length):
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"""Read multiple bytes"""
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"""Read multiple bytes"""
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READ_SINGLE = get_addr["READ_SINGLE"]
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READ_SINGLE = get_addr("READ_SINGLE")
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READ_BURST = get_addr["READ_BURST"]
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READ_BURST = get_addr("READ_BURST")
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return spi.xfer2([addr | READ_SINGLE | READ_BURST] + [0x00] * length)
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return spi.xfer2([addr | READ_SINGLE | READ_BURST] + [0x00] * length)
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@ -18,26 +18,28 @@ def read_fifo(spi):
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def receive_packet(spi):
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def receive_packet(spi):
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# Flush RX FIFO
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SFRX = get_addr("SFRX")
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SFRX = get_addr("SFRX")
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strobe(spi, SFRX) # SFRX
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RXBYTES = get_addr("RXBYTES")
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SRX = get_addr("SRX")
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SRX = get_addr( "SRX")
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# Flush RX FIFO
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strobe(spi, SFRX)
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time.sleep(0.5) # 1 ms delay to allow flush
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# Go into RX mode
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# Go into RX mode
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strobe(spi, SRX) # SRX
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strobe(spi, SRX)
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# Wait for data (use GDO0 in real app)
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# Wait for data (use GDO0 in real app)
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time.sleep(0.5)
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sleep(0.5)
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# Check RXBYTES
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# Check RXBYTES
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RXBYTES = get_addr( "RXBYTES")
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rx_bytes = read_register(spi, RXBYTES) & 0x7F
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timeout = time.time() + 2 # 2-second timeout
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if rx_bytes == 0:
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while time.time() < timeout:
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print("No data received.")
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rx_bytes = read_register(spi, RXBYTES) & 0x7F
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return None
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if rx_bytes > 0:
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data = read_fifo(spi)
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print(f"Received: {data}")
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return data
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time.sleep(0.01)
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# Read data
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print("Timeout: no data received.")
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# RXFIFO = get_addr("RXFIFO")
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data = read_fifo(spi) # 0x3F = RX FIFO
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print(f"Received: {data}")
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return data
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5
util.py
5
util.py
@ -45,17 +45,18 @@ def init_regs(spi):
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addr = get_addr(reg_name)
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addr = get_addr(reg_name)
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write_reg(spi, addr, value)
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write_reg(spi, addr, value)
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def test_read_write_reg(spi):
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def test_read_write_reg(spi, dbg=False):
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FIFOTHR = get_addr("FIFOTHR")
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FIFOTHR = get_addr("FIFOTHR")
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initial_val = read_register(spi, FIFOTHR)
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initial_val = read_register(spi, FIFOTHR)
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test_value = initial_val + 1
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test_value = initial_val + 1
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write_reg(spi, FIFOTHR, test_value)
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write_reg(spi, FIFOTHR, test_value)
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check = read_register(spi, FIFOTHR)
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check = read_register(spi, FIFOTHR)
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write_reg(spi, FIFOTHR, initial_val)
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write_reg(spi, FIFOTHR, initial_val)
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if check != test_value:
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if(dbg):
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print("initial value ", initial_val)
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print("initial value ", initial_val)
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print("test value ", test_value)
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print("test value ", test_value)
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print("check ",check)
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print("check ",check)
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elif (not dbg and (check != test_value)):
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raise Exception("Test Read+Write failed")
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raise Exception("Test Read+Write failed")
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return check == test_value
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return check == test_value
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