diff --git a/main.py b/main.py index d872d33..ddf866d 100644 --- a/main.py +++ b/main.py @@ -1,7 +1,10 @@ import spidev from util import * from receive import receive_packet + debug = True +GDO0_PIN=23, +GDO2_PIN=24 def menu(): print("\nMenu") @@ -12,35 +15,44 @@ def menu(): print("5: Run Read+Write test") print("0: Quit") + if __name__ == "__main__": + + init_gpio(GDO0_PIN, GDO2_PIN) + spi = spidev.SpiDev() spi.open(0, 0) # Bus 0, CE0 (Pin 24) - spi.max_speed_hz = 8000000 # Safe start speed + # spi.max_speed_hz = 8_000_000 # Safe start speed + spi.max_speed_hz = 100_000 # Safe start speed + spi.mode = 0b00 # SPI mode 0 stop = False - print("Sending SRES (reset)...") + print_gdo_state(GDO0_PIN, GDO2_PIN) + + # print("Sending SRES (reset)...") spi.xfer2([SRES]) sleep(0.5) - print("Sending SNOP (no-op)...") + # print("Sending SNOP (no-op)...") status = spi.xfer2([SNOP])[0] print(f"Status byte: 0x{status:02X}") + # print("Reading MARCSTATE...") + marc = spi.xfer2([MARCSTATE| 0x80, 0x00])[0] + print(f"Marcstate byte: 0x{marc:02X}") + print("Reading VERSION register...") version = read_register(spi, VERSION) - print(f"CC2500 VERSION register: 0x{version:02X}") - - test_read_write_reg(spi) - - init_regs(spi) - sleep(0.1) - - + print(f"CC2500 VERSION register: 0x{version:02X}") reg_name = "" reg_hex_val = "" try: + # if version != 0x0F: + # raise Exception("Expected Version was 0x0F!! Quitting") + test_read_write_reg(spi) + init_regs(spi) while not stop: menu() cmd = int(input("$: ")) @@ -60,7 +72,7 @@ if __name__ == "__main__": value_check = read_register(spi,addr) print("Updated Value: " + hex(value) +" == " + str(value)) elif cmd == 3: - dump_regs(spi) + dump_regs(spi, True) elif cmd == 4: receive_packet(spi) elif cmd == 5: @@ -70,4 +82,6 @@ if __name__ == "__main__": print("Invalid command") finally: print("Closing SPI...") + sleep(0.1) spi.close() + sleep(0.1) diff --git a/transmit.py b/transmit.py index 124b136..83f9fdd 100644 --- a/transmit.py +++ b/transmit.py @@ -1,17 +1,22 @@ -def burst_write(addr, data): +from util import strobe, get_addr + +def burst_write(spi, addr, data): """Write multiple bytes to FIFO or registers""" - BURST = 0x40 + BURST = get_addr("BURST") spi.xfer2([addr | BURST] + data) def send_packet(data): # Flush TX FIFO - strobe(0x3B) # SFTX + SFTX = get_addr("SFTX") + strobe(SFTX) # Load data to TX FIFO (fixed length) - burst_write(0x3F, data) # 0x3F = TX FIFO + TXFIFO = get_addr("TXFIFO") + burst_write(TXFIFO, data) # 0x3F = TX FIFO # Strobe STX to transmit - strobe(0x35) # STX + STX = get_addr("STX") + strobe(STX) # STX print(f"Sent: {data}") diff --git a/util.py b/util.py index 20754ed..aa80c06 100644 --- a/util.py +++ b/util.py @@ -1,5 +1,6 @@ from init_regs_value import init_regs_value from regs_addr import regs_addr +import RPi.GPIO as GPIO import time CONFIG_REGS = regs_addr["CONFIG_REGS"] STROBES = regs_addr["STROBES"] @@ -10,6 +11,33 @@ ACCESS = regs_addr["ACCESS"] SRES = STROBES["SRES"] SNOP = STROBES["SNOP"] VERSION = STATUS["VERSION"] +MARCSTATE = STATUS["MARCSTATE"] + +def init_gpio(GDO0_PIN=23, GDO2_PIN=24): + # Use BCM numbering + GPIO.setmode(GPIO.BCM) + + # Set up GPIO 23 and 24 as inputs + # GPIO.setup(GDO0_PIN, GPIO.IN) + # GPIO.setup(GDO2_PIN, GPIO.IN) + GPIO.setup(GDO0_PIN, GPIO.IN, pull_up_down=GPIO.PUD_DOWN) + GPIO.setup(GDO2_PIN, GPIO.IN, pull_up_down=GPIO.PUD_DOWN) + + +# def clear_csn(): +# CSN_PIN = 8 # CE0 = GPIO8 (Pin 24) +# GPIO.setmode(GPIO.BCM) +# GPIO.setup(CSN_PIN, GPIO.OUT) +# sleep(0.1) +# GPIO.output(CSN_PIN, GPIO.HIGH) +# sleep(0.1) + +def print_gdo_state(GDO0_PIN=23, GDO2_PIN=24): + gdo0 = GPIO.input(23) # Reads 1 or 0 + gdo2 = GPIO.input(24) + print(f"GDO0 (GPIO23): {gdo0}, GDO2 (GPIO24): {gdo2}") + sleep(0.1) + def get_addr(name): addr = "" @@ -26,15 +54,18 @@ def get_addr(name): def strobe(spi, command): """Send a command strobe to CC2500""" spi.xfer2([command]) + sleep(0.1) def write_reg(spi, addr, value): """Write single byte to a register""" spi.xfer2([addr, value]) + sleep(0.1) def read_register(spi, addr): READ_SINGLE = get_addr("READ_SINGLE") # Send address | 0x80 (read), then 0x00 dummy to clock in response response = spi.xfer2([READ_SINGLE | addr, 0x00]) + sleep(0.1) return response[1] def disable_crc(spi): @@ -52,20 +83,26 @@ def test_read_write_reg(spi, dbg=False): write_reg(spi, FIFOTHR, test_value) check = read_register(spi, FIFOTHR) write_reg(spi, FIFOTHR, initial_val) - if(dbg): + if(check != test_value): print("initial value ", initial_val) print("test value ", test_value) print("check ",check) - elif (not dbg and (check != test_value)): - raise Exception("Test Read+Write failed") + if(not dbg): + raise Exception("Test Read+Write failed") return check == test_value -def dump_regs(spi): - for reg_type, reg_data in regs_addr.items(): - for reg_name, reg_addr in reg_data.items(): +def dump_regs(spi, cfgonly = False): + if cfgonly: + for reg_name, reg_addr in CONFIG_REGS.items(): name :str = reg_name value = read_register(spi, reg_addr) print((name+":").ljust(15) +hex(value).ljust(4)+"\t"+str(value)) + else: + for reg_type, reg_data in regs_addr.items(): + for reg_name, reg_addr in reg_data.items(): + name :str = reg_name + value = read_register(spi, reg_addr) + print((name+":").ljust(15) +hex(value).ljust(4)+"\t"+str(value)) def sleep(t): return time.sleep(t) \ No newline at end of file