diff --git a/cc2500_init.json b/cc2500_init.json index 6fc3332..3ac1f60 100644 --- a/cc2500_init.json +++ b/cc2500_init.json @@ -3,8 +3,8 @@ "FIFOTHR" : { "hex":"0x47", "dec":71}, "PKTCTRL0": { "hex":"0x05", "dec":5}, "FREQ2" : { "hex":"0x5D", "dec":93}, - "FREQ1" : { "hex":"0x93", "dec":147}, - "FREQ0" : { "hex":"0xB1", "dec":177}, + "FREQ1" : { "hex":"0xD1", "dec":209}, + "FREQ0" : { "hex":"0x4A", "dec":74}, "MDMCFG4" : { "hex":"0x0D", "dec":13}, "MDMCFG3" : { "hex":"0x3B", "dec":59}, "MDMCFG2" : { "hex":"0x73", "dec":115}, diff --git a/read.py b/read.py index 7505728..cae7495 100644 --- a/read.py +++ b/read.py @@ -2,9 +2,6 @@ import spidev import time import json -# Example register to read (e.g., version) -VERSION_REG = 0xF1 # CC2500 version register (0xF1 is 0x31 | 0xC0 for read + burst) - # Initialize SPI global spi global init_data @@ -47,7 +44,7 @@ def read_register(addr): def init_cc2500(): spi.open(0, 0) # Bus 0, CE0 (Pin 24) - spi.max_speed_hz = 500000 # Safe start speed + spi.max_speed_hz = 2000000 # Safe start speed spi.mode = 0b00 # SPI mode 0 print("Sending SRES (reset)...") @@ -97,13 +94,13 @@ def receive_packet(): return None # Read data - data = burst_read(0x3F, rx_bytes) # 0x3F = RX FIFO + RXFIFO = MEMORY["RXFIFO"]["dec"] + data = burst_read(RXFIFO, rx_bytes) # 0x3F = RX FIFO print(f"Received: {data}") return data def test_read_write_reg(): - # FIFOTHR = CONFIG_REGS["FIFOTHR"]["dec"] - FIFOTHR = 0x03 + FIFOTHR = CONFIG_REGS["FIFOTHR"]["dec"] print("reg ", hex(FIFOTHR)) initial_val = read_register(FIFOTHR) test_value = initial_val + 1 @@ -152,7 +149,7 @@ if __name__ == "__main__": for reg_name, values in init_data.items(): addr_dec = regs_data["CONFIG_REGS"][reg_name]["dec"] - addr_hex = regs_data["CONFIG_REGS"][reg_name]["dec"] + addr_hex = regs_data["CONFIG_REGS"][reg_name]["hex"] value_hex = values["hex"] value_dec = values["dec"] # print(addr) @@ -160,7 +157,9 @@ if __name__ == "__main__": # print("writing "+str(addr_hex) + " to "+str(addr_dec)) write_reg(addr_dec, value_dec) print("Read + Write test ", test_read_write_reg()) - while True: - receive_packet() - time.sleep(1) - spi.close() + try: + while True: + receive_packet() + time.sleep(1) + finally: + spi.close()