Compare commits

...

2 Commits

Author SHA1 Message Date
David Westgate
077674e19b RX signal strength workingish 2025-04-11 18:33:22 -07:00
David Westgate
7731cd7288 framework of TX functionality 2025-04-11 17:29:50 -07:00
5 changed files with 63 additions and 29 deletions

View File

@ -25,12 +25,12 @@ The implementation here uses CC2500 register values which intend to mimic my [Gi
| CSN | CE0 (Chip Select) | Pin 24 | GPIO 8 | | CSN | CE0 (Chip Select) | Pin 24 | GPIO 8 |
| SO | MISO | Pin 21 | GPIO 9 | | SO | MISO | Pin 21 | GPIO 9 |
### Optional Pins ### Interrupt Pins
| CC2500 Pin | Function | Raspberry Pi GPIO Pin | GPIO Number | | CC2500 Pin | Function | Raspberry Pi GPIO Pin | GPIO Number |
|------------|-------------------------------------------|-------------------------------|-------------| |------------|-------------------------------------------|-------------------------------|-------------|
| GDO0 | Interrupt/Data Ready | Pin 12 | GPIO 18 | | GDO0 | Interrupt/Data Ready | Pin 11 | GPIO 17 |
| GDO2 | Additional Interrupt/Data Line | Pin 22 | GPIO 25 | | GDO2 | Additional Interrupt/Data Line | Pin 23 | GPIO 27 |
### Power Amplifier Pins (If Applicable) ### Power Amplifier Pins (If Applicable)

View File

@ -21,7 +21,8 @@
# Whitening = false # Whitening = false
init_regs_value = { init_regs_value = {
"IOCFG0" : 0x06, # 6 - GDO0OUTPUT PIN CONFIGURATION "IOCFG0" : 0x06, # 6 - GDO0OUTPUT PIN CONFIGURATION
"PKTCTRL0": 0x05, # 5 - PACKET AUTOMATION CONTROL "PKTCTRL0": 0b00000001,# 5 - PACKET AUTOMATION CONTROL
"PKTCTRL1": 0b00000100,# 4 - PACKET AUTOMATION CONTROL
"FSCTRL1" : 0x12, # 18 - FREQUENCY SYNTHESIZER CONTROL "FSCTRL1" : 0x12, # 18 - FREQUENCY SYNTHESIZER CONTROL
"FREQ1" : 0x20, # 32 - FREQUENCY CONTROL WORD, MIDDLE BYTE "FREQ1" : 0x20, # 32 - FREQUENCY CONTROL WORD, MIDDLE BYTE
"FREQ0" : 0x11, # 17 - FREQUENCY CONTROL WORD, LOW BYTE "FREQ0" : 0x11, # 17 - FREQUENCY CONTROL WORD, LOW BYTE

10
main.py
View File

@ -1,6 +1,7 @@
import spidev import spidev
from util import print_gdo_state, sleep, get_addr, dump_regs, debug, GDO0_PIN, GDO2_PIN from util import print_gdo_state, sleep, get_addr, dump_regs, debug, GDO0_PIN, GDO2_PIN
from receive import rx_data_rf from receive import rx_data_rf
from transmit import transmit_packet
from common import reset, setup_spi, setup_gpio, read_register, test_read_write_reg, init_cc_2500, write_reg, SRES, SNOP, MARCSTATE, VERSION from common import reset, setup_spi, setup_gpio, read_register, test_read_write_reg, init_cc_2500, write_reg, SRES, SNOP, MARCSTATE, VERSION
@ -11,8 +12,9 @@ def menu():
print("2: Write reg hex value by name") print("2: Write reg hex value by name")
print("3: Dump registers") print("3: Dump registers")
print("4: rx_data_rf") print("4: rx_data_rf")
print("5: Run Read+Write test") print("5: transmit_packet")
print("6: Print GDO state") print("6: Run Read+Write test")
print("7: Print GDO state")
print("0: Quit") print("0: Quit")
@ -52,9 +54,11 @@ if __name__ == "__main__":
while(True): while(True):
rx_data_rf(spi) rx_data_rf(spi)
elif cmd == 5: elif cmd == 5:
transmit_packet(spi)
elif cmd == 6:
res = test_read_write_reg(spi, True) res = test_read_write_reg(spi, True)
print("Test result : "+str(res)) print("Test result : "+str(res))
elif cmd == 6: elif cmd == 7:
print_gdo_state(GDO0_PIN, GDO2_PIN) print_gdo_state(GDO0_PIN, GDO2_PIN)
else: else:
print("Invalid command") print("Invalid command")

View File

@ -6,6 +6,33 @@ SIDLE = get_addr('SIDLE')
SFRX = get_addr('SFRX') SFRX = get_addr('SFRX')
SRX = get_addr('SRX') SRX = get_addr('SRX')
RXFIFO = get_addr('RXFIFO') RXFIFO = get_addr('RXFIFO')
RSSI = get_addr('RSSI')
def print_packet(spi, packet_length):
for i in range(packet_length):
print(f", byte: {0}: 0x{1}", i, read_register(spi, RXFIFO))
#TODO
def save_packet():
print()
def get_rssi_from_pkt(packet):
if len(packet) < 2:
raise ValueError("Packet too short to contain RSSI and status bytes.")
rssi_raw = packet[-2] # Second-to-last byte is RSSI
return rssi_raw
def get_rssi_from_reg(spi):
return read_register(spi, RSSI)
def get_signal_strength_rssi_raw(rssi_raw):
if rssi_raw >= 128:
rssi_dec = rssi_raw - 256
else:
rssi_dec = rssi_raw
return rssi_dec / 2.0 - 74 # According to CC2500 datasheet
def flush_rx(spi): def flush_rx(spi):
# Make sure that the radio is in IDLE state before flushing the FIFO # Make sure that the radio is in IDLE state before flushing the FIFO
@ -21,21 +48,24 @@ def rx_data_rf(spi):
strobe(spi, SRX) strobe(spi, SRX)
gdo2_state = False gdo2_state = False
count = 0 count = 0
strength = 0
while(gdo2_state == False): while(gdo2_state == False):
gdo2_state = digital_read(GDO2_PIN) gdo2_state = digital_read(GDO2_PIN)
delay(1) delay(1)
count = count+1 count = count+1
if count > 1000: if count > 1000:
flush_rx(spi) flush_rx(spi)
print("ERR NO DATA") # print("ERR NO DATA")
return return
while(gdo2_state == True): while(gdo2_state == True):
gdo2_state = digital_read(GDO2_PIN) gdo2_state = digital_read(GDO2_PIN)
delay(100) delay(100)
packet_length: int = read_register(spi, RXFIFO) packet_length: int = read_register(spi, RXFIFO)
print("Packet Length {0}".format(packet_length)) # print("Packet Length {0}".format(packet_length))
for i in range(packet_length): packet: list = [read_register(spi, RXFIFO) for _ in range(packet_length)]
print(f", byte: {0}: 0x{1}", i, read_register(spi, RXFIFO)) rssi_raw = get_rssi_from_pkt(packet)
strength = get_signal_strength_rssi_raw(rssi_raw)
print("Length: {0} bytes\t Signal: {1} dBm".format(packet_length, strength) )
# Make sure that the radio is in IDLE state before flushing the FIFO # Make sure that the radio is in IDLE state before flushing the FIFO
# (Unless RXOFF_MODE has been changed, the radio should be in IDLE state at this point) # (Unless RXOFF_MODE has been changed, the radio should be in IDLE state at this point)

View File

@ -1,22 +1,21 @@
from . import strobe, get_addr from common import strobe, write_burst
from util import get_addr
def burst_write(spi, addr, data):
"""Write multiple bytes to FIFO or registers"""
BURST = get_addr("BURST")
spi.xfer2([addr | BURST] + data)
def send_packet(data): SIDLE = get_addr('SIDLE')
# Flush TX FIFO SFTX = get_addr('SFTX')
SFTX = get_addr("SFTX") STX = get_addr('STX')
strobe(SFTX) WRITE_BURST = get_addr("WRITE_BURST")
TXFIFO_BURST = 0x7F
# Load data to TX FIFO (fixed length) def transmit_packet(spi):
TXFIFO = get_addr("TXFIFO") strobe(spi, SIDLE)
burst_write(TXFIFO, data) # 0x3F = TX FIFO strobe(spi, SFTX)
data = [0] * 5
data[0] = 5
data[1] = 1
data[2] = 2
data[3] = 3
data[4] = 4
write_burst(spi, TXFIFO_BURST, data)
# Strobe STX to transmit
STX = get_addr("STX")
strobe(STX) # STX
print(f"Sent: {data}")