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No commits in common. "a301cc5ea109f5a21b7d795794970b12449d2b39" and "077674e19b5a7717855b837626e0653a79cca2e3" have entirely different histories.
a301cc5ea1
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077674e19b
2
.gitignore
vendored
2
.gitignore
vendored
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saved_packets/*
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src/__pycache__
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3
.vscode/settings.json
vendored
3
.vscode/settings.json
vendored
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{
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"python.analysis.stubPath": "./typings"
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}
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@ -106,4 +106,4 @@ The known frequency range is 2400 – 2483.5 MHz, and my SDR has a 20 MHZ bandwi
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## Run
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## Run
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`python3 -m src.main`
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`python3 read.py`
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BIN
__pycache__/init_regs_value.cpython-311.pyc
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BIN
__pycache__/init_regs_value.cpython-311.pyc
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__pycache__/regs_addr.cpython-311.pyc
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__pycache__/regs_addr.cpython-311.pyc
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__pycache__/util.cpython-311.pyc
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__pycache__/util.cpython-311.pyc
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import spidev
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import spidev
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import RPi.GPIO as GPIO
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import RPi.GPIO as GPIO
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from .util import sleep, get_addr
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from util import sleep, get_addr
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from .init_regs_value import init_regs_value
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from init_regs_value import init_regs_value
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from .regs_addr import regs_addr
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from regs_addr import regs_addr
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CONFIG_REGS = regs_addr["CONFIG_REGS"]
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CONFIG_REGS = regs_addr["CONFIG_REGS"]
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STROBES = regs_addr["STROBES"]
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STROBES = regs_addr["STROBES"]
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STATUS = regs_addr["STATUS"]
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STATUS = regs_addr["STATUS"]
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@ -83,7 +83,7 @@ def reset(spi):
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version = read_register(spi, VERSION)
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version = read_register(spi, VERSION)
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print(f"CC2500 VERSION register: 0x{version:02X}")
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print(f"CC2500 VERSION register: 0x{version:02X}")
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# if version != 0x2F:
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# if version != 0x2F:
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# raise Exception("Expected Version was 0x2F!! Quitting")
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# raise Exception("Expected Version was 0x0F!! Quitting")
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def test_read_write_reg(spi, dbg=False):
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def test_read_write_reg(spi, dbg=False):
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12
freq.txt
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12
freq.txt
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Handheld Init
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2.4312 GHZ (mid)
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2.439256 (strong)
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2.447 GHZ (strong)
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2.4632 GHZ (strong)
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2.471 GHZ (weak)
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Test Pts
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2410000.000
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2430000.000
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2450000.000
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2470000.000
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import spidev
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import spidev
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from .util import print_gdo_state, sleep, get_addr, dump_regs, debug, GDO0_PIN, GDO2_PIN
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from util import print_gdo_state, sleep, get_addr, dump_regs, debug, GDO0_PIN, GDO2_PIN
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from .receive import rx_data_rf
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from receive import rx_data_rf
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from .transmit import transmit_packet
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from transmit import transmit_packet
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from .common import reset, setup_spi, setup_gpio, read_register, test_read_write_reg, init_cc_2500, write_reg, SRES, SNOP, MARCSTATE, VERSION
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from common import reset, setup_spi, setup_gpio, read_register, test_read_write_reg, init_cc_2500, write_reg, SRES, SNOP, MARCSTATE, VERSION
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@ -1,8 +1,6 @@
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from datetime import datetime
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from util import sleep, get_addr, digital_read, GDO0_PIN, GDO2_PIN, debug, delay
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from pathlib import Path
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from .util import sleep, get_addr, digital_read, GDO0_PIN, GDO2_PIN, debug, delay
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import time
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import time
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from .common import strobe, read_register
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from common import strobe, read_register
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SIDLE = get_addr('SIDLE')
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SIDLE = get_addr('SIDLE')
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SFRX = get_addr('SFRX')
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SFRX = get_addr('SFRX')
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@ -14,21 +12,9 @@ def print_packet(spi, packet_length):
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for i in range(packet_length):
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for i in range(packet_length):
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print(f", byte: {0}: 0x{1}", i, read_register(spi, RXFIFO))
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print(f", byte: {0}: 0x{1}", i, read_register(spi, RXFIFO))
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# Save packet to a timestamped binary file
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#TODO
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def save_packet(packet: list):
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def save_packet():
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# Create directory to store packets if it doesn't exist
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print()
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packet_dir = Path("saved_packets")
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packet_dir.mkdir(parents=True, exist_ok=True)
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# Create timestamped filename
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timestamp = datetime.now().strftime("%Y%m%d_%H%M%S")
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filename = packet_dir / f"packet_{timestamp}.bin"
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# Save packet as binary data
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with open(filename, "wb") as f:
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f.write(bytearray(packet))
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print(f"Packet saved to {filename}")
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def get_rssi_from_pkt(packet):
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def get_rssi_from_pkt(packet):
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@ -75,13 +61,57 @@ def rx_data_rf(spi):
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gdo2_state = digital_read(GDO2_PIN)
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gdo2_state = digital_read(GDO2_PIN)
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delay(100)
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delay(100)
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packet_length: int = read_register(spi, RXFIFO)
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packet_length: int = read_register(spi, RXFIFO)
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# print("Packet Length {0}".format(packet_length))
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packet: list = [read_register(spi, RXFIFO) for _ in range(packet_length)]
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packet: list = [read_register(spi, RXFIFO) for _ in range(packet_length)]
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rssi_raw = get_rssi_from_pkt(packet)
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rssi_raw = get_rssi_from_pkt(packet)
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strength = get_signal_strength_rssi_raw(rssi_raw)
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strength = get_signal_strength_rssi_raw(rssi_raw)
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print("Length: {0} bytes\t Signal: {1} dBm".format(packet_length, strength) )
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print("Length: {0} bytes\t Signal: {1} dBm".format(packet_length, strength) )
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save_packet(packet)
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# Make sure that the radio is in IDLE state before flushing the FIFO
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# Make sure that the radio is in IDLE state before flushing the FIFO
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# (Unless RXOFF_MODE has been changed, the radio should be in IDLE state at this point)
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# (Unless RXOFF_MODE has been changed, the radio should be in IDLE state at this point)
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strobe(spi, SIDLE)
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strobe(spi, SIDLE)
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# Flush RX FIFO
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# Flush RX FIFO
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strobe(spi, SFRX)
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strobe(spi, SFRX)
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# def burst_read(spi, addr, length):
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# """Read multiple bytes"""
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# READ_SINGLE = get_addr("READ_SINGLE")
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# READ_BURST = get_addr("READ_BURST")
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# return spi.xfer2([addr | READ_SINGLE | READ_BURST] + [0x00] * length)
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# def read_fifo(spi):
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# # Burst read RX FIFO
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# READ_BURST = get_addr("READ_BURST")
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# RXFIFO = get_addr("RXFIFO")
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# fifo = spi.xfer2([RXFIFO | READ_BURST] + [0x00]*64) # Max 64 bytes
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# return fifo[1:]
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# def receive_packet(spi):
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# SFRX = get_addr("SFRX")
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# RXBYTES = get_addr("RXBYTES")
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# SRX = get_addr("SRX")
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# # Flush RX FIFO
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# strobe(spi, SFRX)
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# time.sleep(0.5) # 1 ms delay to allow flush
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# # Go into RX mode
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# strobe(spi, SRX)
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# # Wait for data (use GDO0 in real app)
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# sleep(0.5)
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# # Check RXBYTES
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# timeout = time.time() + 2 # 2-second timeout
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# while time.time() < timeout:
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# rx_bytes = read_register(spi, RXBYTES) & 0x7F
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# if rx_bytes > 0:
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# data = read_fifo(spi)
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# print(f"Received: {data}")
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# return data
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# time.sleep(0.01)
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# print("Timeout: no data received.")
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@ -1,5 +1,5 @@
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from .common import strobe, write_burst
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from common import strobe, write_burst
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from .util import get_addr
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from util import get_addr
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SIDLE = get_addr('SIDLE')
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SIDLE = get_addr('SIDLE')
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@ -1,6 +0,0 @@
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class SpiDev:
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def open(self, bus: int, device: int) -> None: ...
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def close(self) -> None: ...
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def xfer2(self, data: list[int]) -> list[int]: ...
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max_speed_hz: int
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mode: int
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from .regs_addr import regs_addr
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from regs_addr import regs_addr
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import RPi.GPIO as GPIO
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import RPi.GPIO as GPIO
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import time
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import time
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debug = True
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debug = True
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@ -19,7 +19,14 @@ def print_gdo_state(GDO0_PIN=17, GDO2_PIN=27):
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sleep(0.1)
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sleep(0.1)
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def digital_read(GDO_PIN: int):
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def digital_read(GDO_PIN: int):
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return GPIO.input(GDO_PIN)
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bit = GPIO.input(GDO_PIN)
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# print("bit " + str(bit))
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if bit == 1:
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return True
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elif bit == 0:
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return False
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else:
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raise Exception("Unexpected digital read GDO_PIN{GDO_PIN} {bit}")
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def get_addr(name):
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def get_addr(name):
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addr = ""
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addr = ""
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31
wiring.txt
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31
wiring.txt
Normal file
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CC2500 Pins to Raspberry Pi GPIO Pins
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GND (CC2500) → Ground (Pin 6 on Raspberry Pi GPIO header)
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VCC (CC2500) → 3.3V Power (Pin 1 or Pin 17 on Raspberry Pi GPIO header)
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Ensure the CC2500 module operates at 3.3V. Connecting it to 5V may damage it.
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SPI Pins:
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SI (CC2500) → MOSI (GPIO 10) (Pin 19 on Raspberry Pi GPIO header)
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SCK (CC2500) → SCLK (GPIO 11) (Pin 23 on Raspberry Pi GPIO header)
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CSN (CC2500) → CE0 (GPIO 8) (Pin 24 on Raspberry Pi GPIO header)
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This is the Chip Select line.
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SO (CC2500) → MISO (GPIO 9) (Pin 21 on Raspberry Pi GPIO header)
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Optional Pins:
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GDO0 (CC2500) → Any GPIO Pin (e.g., GPIO 18) (Pin 12 on Raspberry Pi GPIO header)
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Use this for interrupt handling or data-ready signals if required.
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GDO2 (CC2500) → Any GPIO Pin (e.g., GPIO 25) (Pin 22 on Raspberry Pi GPIO header)
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Additional interrupt or data pin.
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Power Amplifier Pins (If Applicable):
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PA_EN (CC2500) → Any GPIO Pin (Optional, depending on whether you control the amplifier externally or not).
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PA_EX (CC2500) → Not Connected (unless needed for a specific configuration)
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