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script improvements

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This commit is contained in:
David Westgate 2025-04-09 19:53:12 -07:00
parent 21e95b8d3a
commit e6e9efd73e
2 changed files with 13 additions and 14 deletions
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4
cc2500_init.json
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@ -3,8 +3,8 @@
"FIFOTHR" : { "hex":"0x47", "dec":71}, "FIFOTHR" : { "hex":"0x47", "dec":71},
"PKTCTRL0": { "hex":"0x05", "dec":5}, "PKTCTRL0": { "hex":"0x05", "dec":5},
"FREQ2" : { "hex":"0x5D", "dec":93}, "FREQ2" : { "hex":"0x5D", "dec":93},
"FREQ1" : { "hex":"0x93", "dec":147}, "FREQ1" : { "hex":"0xD1", "dec":209},
"FREQ0" : { "hex":"0xB1", "dec":177}, "FREQ0" : { "hex":"0x4A", "dec":74},
"MDMCFG4" : { "hex":"0x0D", "dec":13}, "MDMCFG4" : { "hex":"0x0D", "dec":13},
"MDMCFG3" : { "hex":"0x3B", "dec":59}, "MDMCFG3" : { "hex":"0x3B", "dec":59},
"MDMCFG2" : { "hex":"0x73", "dec":115}, "MDMCFG2" : { "hex":"0x73", "dec":115},

15
read.py
View File

@ -2,9 +2,6 @@ import spidev
import time import time
import json import json
# Example register to read (e.g., version)
VERSION_REG = 0xF1 # CC2500 version register (0xF1 is 0x31 | 0xC0 for read + burst)
# Initialize SPI # Initialize SPI
global spi global spi
global init_data global init_data
@ -47,7 +44,7 @@ def read_register(addr):
def init_cc2500(): def init_cc2500():
spi.open(0, 0) # Bus 0, CE0 (Pin 24) spi.open(0, 0) # Bus 0, CE0 (Pin 24)
spi.max_speed_hz = 500000 # Safe start speed spi.max_speed_hz = 2000000 # Safe start speed
spi.mode = 0b00 # SPI mode 0 spi.mode = 0b00 # SPI mode 0
print("Sending SRES (reset)...") print("Sending SRES (reset)...")
@ -97,13 +94,13 @@ def receive_packet():
return None return None
# Read data # Read data
data = burst_read(0x3F, rx_bytes) # 0x3F = RX FIFO RXFIFO = MEMORY["RXFIFO"]["dec"]
data = burst_read(RXFIFO, rx_bytes) # 0x3F = RX FIFO
print(f"Received: {data}") print(f"Received: {data}")
return data return data
def test_read_write_reg(): def test_read_write_reg():
# FIFOTHR = CONFIG_REGS["FIFOTHR"]["dec"] FIFOTHR = CONFIG_REGS["FIFOTHR"]["dec"]
FIFOTHR = 0x03
print("reg ", hex(FIFOTHR)) print("reg ", hex(FIFOTHR))
initial_val = read_register(FIFOTHR) initial_val = read_register(FIFOTHR)
test_value = initial_val + 1 test_value = initial_val + 1
@ -152,7 +149,7 @@ if __name__ == "__main__":
for reg_name, values in init_data.items(): for reg_name, values in init_data.items():
addr_dec = regs_data["CONFIG_REGS"][reg_name]["dec"] addr_dec = regs_data["CONFIG_REGS"][reg_name]["dec"]
addr_hex = regs_data["CONFIG_REGS"][reg_name]["dec"] addr_hex = regs_data["CONFIG_REGS"][reg_name]["hex"]
value_hex = values["hex"] value_hex = values["hex"]
value_dec = values["dec"] value_dec = values["dec"]
# print(addr) # print(addr)
@ -160,7 +157,9 @@ if __name__ == "__main__":
# print("writing "+str(addr_hex) + " to "+str(addr_dec)) # print("writing "+str(addr_hex) + " to "+str(addr_dec))
write_reg(addr_dec, value_dec) write_reg(addr_dec, value_dec)
print("Read + Write test ", test_read_write_reg()) print("Read + Write test ", test_read_write_reg())
try:
while True: while True:
receive_packet() receive_packet()
time.sleep(1) time.sleep(1)
finally:
spi.close() spi.close()